Towards Reducing Reversible Circuit Synthesis Time
Publication Type
Conference Paper

Synthesizing reversible circuits is still an important issue in the area of low power consumption circuit design. Several algorithms have been proposed in the field in order to synthesize reversible circuits with minimum cost in terms of line number and quantum cost with sacrificing the objective of reducing the synthesis time. However, for large scale circuits to be synthesized, long synthesis time is required since some algorithms perform iterative synthesis during the optimization process. Binary Decision Diagram (BDD) is considered a step forward in this field due to the minimization of cost achieved. In this work, we are moving from the BDD node-based to subtree-based mapping in the process of reversible circuit synthesis. We propose considering a complete BDD subtree to be converted in one step into a cascade of reversible gates instead of single node mapping in order to minimize the synthesis time. All possible subtrees are saved in a two column lookup table of subtrees and their corresponding reversible gates. Theoretically, our proposed algorithm can be more than 2X faster the transitional single node-to-gate synthesis.

Conference Title
Conference: The 2019 IEEE Jordan International Joint Conference on Electrical Engineering and Information Technology (JEEIT)At: Amman/Jordan
Conference Country
Conference Date
Feb. 1, 2019 - Feb. 1, 2019
Conference Sponsor
البنك الاسلامي الاردني, Cisoc, Atypon, Estartam Siemens, Zain
Additional Info
Conference Website