With the continuous shrinking of minimum feature sizes beyond current 193nm wavelength for optical micro lithography, the electronic industry relies on Resolution Enhancement Techniques (RETs) to improve pattern transfer fidelity. Dense layouts suffer from more and more image quality degradation that badly impacts lithographic yield. In this paper, a new intensity based algorithm is proposed to minimize Edge Placement Error (EPE) in low scale features printing through simultaneous shifting of neighboring segments and serifis sizing for corners. Our experimental results show that our algorithm minimizes EPE effectively on the public benchmarks released by IBM for ICCAD 2013 contest.

Conference Title

27th Workshop on Circuits and Systems

Conference Country

Japan

Conference Date

Aug. 5, 2014 - Aug. 8, 2014

Conference Sponsor

IEICE