Reducing Test Power for Embedded Memories
Publication Type
Conference Paper

With the increased number of embedded memories in mobile devices, minimizing the test power becomes a serious concern, especially when parallel testing is applied. Battery will be lost and the entire System on Chip (SoC) is subjected to be damaged if the peak power exceeds the power constraint. This paper proposes a new scheme to reduce the peak power during embedded SRAMs testing in mobile devices. The scheme is based on (a) grouping different memories into clusters based on their word lengths, and (b)scheduling read and write operations in such a way that the consumed power is minimal. Simulation results of a case-of-study show that up to 60% in the peak power reduction can be achieved, at a cost of only one additional clock cycle test time.

Conference Title
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).
Conference Country
Conference Date
Oct. 3, 2011 - Oct. 5, 2011
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