High-level synthesis has become commonplace in many areas of computing such as VLSI design and digital signal processing. However, it is just beginning to receive attention in the area of real-time systems. Given a real-time application and a design library of components, high-level synthesis involves three main steps: (i) estimation of processors and resources required to meet the constraints of the application, (ii) identifying suitable architectures using the components from the design library, and (iii) scheduling application tasks on the selected architecture. In this paper, we focus on the rst and the third steps of this process. Speci cally, we identify key issues in parallelizing these two steps. We then discuss approaches to deal with these issues and present results of our distributed implementation. The results of this implementation on a network of workstations show that considerable speedup in overall runtimes can be achieved by using multiple workstations.

Title

Proceedings of IEEE Real-Time technology And Application Symposium, May 1995.

Publisher

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Publisher Country

Palestine

Publication Type

Both (Printed and Online)

Volume

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Year

1995

Pages

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